I began digital design using programmable array logic (PAL) long before FPGAs became readily available. The usability for design peaked with Altera’s MaxPlus software, and the tools continue to present a challenge. While most of the effort to simplify FPGA design has been from a software perspective, I have chosen a modular and graphical method. The parts and tools are older, but they significantly reduce the learning curve.
These designs have resulted from two experiences: high-speed design, where data arrives faster than it can be processed, and most communications moving to SERDES. The original bus was designed to simplify hardware/software integration.
I have found that using these methods allows me to build upon previous work and quickly create new designs.
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